System Core

The System core contains the essential modules required for the normal operation of the Whizz80. Any missing modules may prevent the Whizz80 computer from functioning correctly.

graph TD; subgraph System Core SYSBUS(System Core) --- POWER(Power) SYSBUS --- CLOCK(Clock) SYSBUS --- MEMORY(Memory Logic) SYSBUS --- IO(I/O Logic) IOBUS(I/O Bridge) --- SYSBUS end

Modules

Each logical module is required to make the system core functional.

Power

The current power design of the Whizz80 has fairly trivial power requirements. Currently only +5v is required and <100 milliamp is required by the system core. Of course the power usage will increase as I/O modules are installed, and depending on their requirements.

Clock

The clock module simply outputs a clock signal to the rest of the system core. It controls the timing of everything in the system core (as well as any I/O modules if required). Currently there are 3 modes planned for the system clock. A manual push button switch that will pump clock cycles into the system. A 2 Hz clock signal can also be generated, slow enough to watch the signals on a logic probe or oscilloscope. Finally a 1 Mhz crystal oscillator to run the system at ‘full speed’. All these signals are controlled by a switch to select the clock cycle the user wants to run the system at.

I have deliberately capped the system speed to 1Mhz in the design. The system core most likely could go faster (my hardware CPU is rated for 10Mhz) but as I'm building this on a breadboard, there can be issues with capacitance and signal integrity with high clock speeds. 1Mhz seems to be a nice speed (I'm not planning on breaking any speed records here!)

Memory Circuits

The memory circuits are used to determine what kind of memory (ROM/RAM) is being accessed. Because there is an even split of memory (32/32) the memory logic is fairly simple.

IO Logic

The IO logic determines what device is being used and sends these signals down the I/O Bus.

CPU Control

The remaining parts of the system-core design center around general CPU control signals.