RAM Module

Connects the RAM chip to the system bus. 32Kb of RAM is currently planned.

graph TD subgraph System Core SYSBUS(System Bus) -.- POWER(Power Module) SYSBUS -.- CLOCK(Clock Module) SYSBUS -.- CPU(CPU Module) SYSBUS === RAM(RAM Module) SYSBUS -.- ROM(ROM Module) IO(I/O Bridge) -.- SYSBUS end style SYSBUS fill:#fff,stroke:#333; style RAM fill:#f96,stroke:#333,stroke-width:4px;