Clock Module

The clock module outputs a clock signal onto the system bus that controls the timing of everything. A simple version of this module might just be an oscillator or a 555 timer, or it could be as complicated as a stepper single shot timer. As long as the output of the clock module can generate a clean square wave.

graph TD subgraph System Core SYSBUS(System Bus) -.- POWER(Power Module) SYSBUS === CLOCK(Clock Module) SYSBUS -.- CPU(CPU Module) SYSBUS -.- RAM(RAM Module) SYSBUS -.- ROM(ROM Module) IO(I/O Bridge) -.- SYSBUS end style SYSBUS fill:#fff,stroke:#333; style CLOCK fill:#f96,stroke:#333,stroke-width:4px;

The clock speed should be limited to 2MHz, and I have no intention of running the Whizz80 computer any faster. I have found that running the clock speed faster than 2MHz can cause unreliable signals to appear of the system bus. I believe this is caused by the transmission line effect. So in theory you could go faster, but it can add to the complication of the design with allowing proper termination of the bus, etc.

I just want a reliable clock speed, not the fastest clock speeds, so this design is to keep things simple.

System Bus Usage

The following lines from the system bus are used by the clock module:

BusLine Label Description
.. .. ..
17 VCC +5v Power source
18 GND Ground
19 /CLOCK Clock signal
.. .. ..
26 /M1 Machine Cycle 1 signal
27 /WAIT Wait State signal
.. .. ..

/M1 and /WAIT are optional and can be used to control the clock (or pause the CPU until the clock is ready).